Qume DataTrak 8 Manual descarregar pdf (Página 13)

SECTION 2 HARDWARE DESCRIPTION

Figure 2-1. Memory Address Detection

2.3 PORT ADDRESS DETECTION

S-100 address lines AO thru A7 are constantly monitored by

the Port Address Detection circuit. This circuit is composed of

IC 3F and part of 3E. See figure 2-2. Switches "PO" and "P1" are

used to vary the selected port address from 40 thru 43 hex. An

address match is indicated by BPA* (Bus - Port Addressed) being

asserted.

SWITCH

ADDRESS

PORT

Open

Figure 2-2.

Port Address Detection

Table 2-2.

Port Address Selection

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 46 47

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Qume DataTrak 8 Manual Página 13